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職責(zé)范圍：1. Physical implementation of advanced technology chips.2. Design methodology development and innovation for advanced technology challenges.3. Be responsible for 22/16/12/10/7/5nm chip implementation for customer’s projects or internal system test chips.4. Be responsible for advanced node PPA benchmark, and solution development.5. EDA tool new features enablement. 6. Customer onsite/offsite supports will be required on demand. 負(fù)責(zé)先進(jìn)芯片技術(shù)的物理實(shí)現(xiàn)。負(fù)責(zé)先進(jìn)技術(shù)之設(shè)計(jì)方法的開發(fā)與創(chuàng)新。負(fù)責(zé)16 / 10 / 7/5納米之客戶項(xiàng)目或內(nèi)部系統(tǒng)測試芯片的實(shí)施。負(fù)責(zé)完善EDA工具及客戶支持。職位要求： 1. MS or above in EE, CS related fields. Experience in APR, physical verification, chip implementation, or CAD development is plus.2. 3 years working experience in chip physical implementation.3. Familiar with Synopsys/Cadence APR tools/flows.4. Familiar with TCL/Perl/Python programming.5. Experience with TSMC advanced technology is plus.6. Proven record in production tape-outs is plus.微電子、計(jì)算機(jī)科學(xué)、電子科學(xué)與技術(shù)等相關(guān)領(lǐng)域知識的碩士含以上人員。具有APR、物理驗(yàn)證、芯片的實(shí)現(xiàn)經(jīng)驗(yàn)及CAD開發(fā)經(jīng)驗(yàn)者優(yōu)先。熟悉Synopsys/Cadence APR 工具及流程。熟悉 tcl/perl 程序。具有TSMC先進(jìn)技術(shù)經(jīng)驗(yàn)的人員優(yōu)先。具有成功流片經(jīng)驗(yàn)優(yōu)先。 職能類別：集成電路IC設(shè)計(jì)/應(yīng)用工程師